Fat Agnus Pin Assignment

Fat Agnus (animation, DMA, clock) chip in Amiga 500+, 600 and 3000.

01-14 RD15-RD2 Register Bus Lines 15 to 2 I/O
15 /INT3 Blitter Ready Interrupt O
16 DMAL Request Audio/Disk DMA I
17 RD1 Register Bus Line 1 I/O
18 /RST Reset I
19 /BLS Blitter Slowdown I
20 /DBR Data Bus Request O
21 RRW DRAM Write/Read O
22 PRW Processor Write/Read I
23 /RGEN RG Enable I
24 /AS Address Strobe I
25 /RAMEN RAM Enable I
26-33 RGA8-RGA1 Register Address Bus 8-1 O
34 28MHZ Master Clock I
35 XCLK Alternate Master Clock I
36 /XCLKEN Master Clock Enable I
37 /CDAC Interted Shifted 7MHz Clock O
38 7MHZ 28MHz Clock Divided by Four O
39 CCKQ Color Clock Delay O
40 CCK Color Clock O
41 TEST Test - Access Registers I
43-51 MA0-MA8 Output Bus Lines 0 to 8 O
52 /LDS Lower Data Strobe I
53 /UDS Upper Data Strobe I
54 /CASL Column Address Strobe Lower O
55 /CASU Column Address Strobe Upper O
56 /RAS1 Row Address Strobe One O
57 /RAS0 Row Address Strobe Zero O
59-77 A19-A1 Address Bus Lines 19 to 1 I
78 /LP Light Pen O
79 /VSY Vertical Sync I/O
80 /CSY Composite Video Sync O
81 /HSY Horizontal Sync I/O
84 RD0 Register  Bus Line 0 I/O

Source: Amiga Hardware Reference Manual

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