Agnus Pin Assignment

Standard Agnus (animation and DMA) chip in Amiga 1000, 2000 and 500.

01-09 D8-D0 Data Bus Lines 8 to 0 I/O
10 VCC +5 Volt I
11 /RES System Reset I
12 /INT3 Interrupt Level 3 O
13 DMAL DMA Request Line I
14 /BLS Blitter Slowdown I
15 /DBR Data Bus Request O
16 /ARW Agnus RAM Write O
17-24 RGA8-RGA1 Register Address Bus 8-1 I/O
25 CCK Color Clock I
26 CCKQ Color Clock Delay I
27 VSS Ground I
28-36 DRA0-DRA8 DRAM Address Bus 0 to 8 O
37 /LP Light Pen Input I
38 /VSY Vertical Sync I/O
39 /CSY Composite Sync O
40 /HSY Horizontal Sync I/O
41 VSS Ground I
42-48 D15-D9 Data Bus Lines 15 to 9 I/O

Source: Amiga Hardware Reference Manual

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