Amiga 1200 Clock Port

Two 40-pin DIL headers, not necessary with all pins.

  P9B (Bottom) P9A (Top)
1 GND Ground GND Ground
2 VCC +5v DC VCC +5v DC
3 DRD0 DRAM Data Bus Bit 0 DRD16 DRAM Data Bus Bit 16
4 DRD15 DRAM Data Bus Bit 15 DRD31 DRAM Data Bus Bit 31
5 DRD1 DRAM Data Bus Bit 1 DRD17 DRAM Data Bus Bit 17
6 DRD14 DRAM Data Bus Bit 14 DRD30 DRAM Data Bus Bit 30
7 DRD2 DRAM Data Bus Bit 2 DRD18 DRAM Data Bus Bit 18
8 DRD13 DRAM Data Bus Bit 13 DRD29 DRAM Data Bus Bit 29
9 DRD3 DRAM Data Bus Bit 3 DRD19 DRAM Data Bus Bit 19
10 DRD12 DRAM Data Bus Bit 12 DRD28 DRAM Data Bus Bit 28
11 DRD4 DRAM Data Bus Bit 4 DRD20 DRAM Data Bus Bit 20
12 DRD11 DRAM Data Bus Bit 11 DRD27 DRAM Data Bus Bit 27
13 DRD5 DRAM Data Bus Bit 5 DRD21 DRAM Data Bus Bit 21
14 DRD10 DRAM Data Bus Bit 10 DRD26 DRAM Data Bus Bit 26
15 DRD6 DRAM Data Bus Bit 6 DRD22 DRAM Data Bus Bit 22
16 DRD9 DRAM Data Bus Bit 9 DRD25 DRAM Data Bus Bit 25
17 DRD7 DRAM Data Bus Bit 7 DRD23 DRAM Data Bus Bit 23
18 DRD8 DRAM Data Bus Bit 8 DRD24 DRAM Data Bus Bit 24
19 GND Ground GND Ground
20 VCC +5v DC VCC +5v DC
21 INT6 Interupt Request _BWE  
22 _SPARE_CS   _ROE  
23 _RTC_CS Real Time Clock CS _BRAS0 Budgie Row Addr. Bit 0
24 _PWR_BAD Power Bad _BRAS1 Budgie Row Addr. Bit 1
25 _IORD IO Read _BCAS_UU Budgie Col. Addr. Strobe
26 _IOWR IO Write _BCAS_UM Budgie Col. Addr. Strobe
27 A5 Address Bus Bit 5 _BCAS_LL Budgie Col. Addr. Strobe
28 A4 Address Bus Bit 4 _BCAS_LM Budgie Col. Addr. Strobe
29 A3 Address Bus Bit 3 BDRA0  
30 A2 Address Bus Bit 2 CCK_A Colour Clock
31 D23 Data Bit 23 BDRA1  
32 D22 Data Bit 22 BDRA8  
33 D21 Data Bit 21 BDRA2  
34 D20 Data Bit 20 BDRA7  
35 D19 Data Bit 19 BDRA3  
36 D18 Data Bit 18 BDRA6  
37 D17 Data Bit 17 BDRA4  
38 D16 Data Bit 16 BDRA5  
39 GND Ground GND Ground
40 _RESET Reset VCC +5v DC

Source: Amiga Hacking Zone

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